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کتاب "Digital system design with VHDL" توسط پروفسور Mark Zwolinski نوشته شده است.
این کتاب با دیدگاه سخت افزاری مطالب را دسته بندی و ارائه کرده است. بنابراین سرفصل هایی که بر اساس مشخصات زبان VHDL نوشته شده باشد در این کتاب نمی بینید بلکه فصول کتاب بر اساس مفاهیم سخت افزاری از قبیل مدارهای ترکیبی، مدارهای ترتیبی و ... فهرست شده اند. در این کتاب به بسیاری از مسائل مهم طراحی از قبیل طراحی برای تست و طراحی سیستم آسنکرون و ... پرداخته شده که اغلب کتاب های VHDL به دلیل ماهیت پیشرفته اینگونه مسائل از آن چشم پوشی کرده اند. این کتاب به دلیل ماهیت سخت افزار گرا، کلیه خصوصیات زبان VHDL از سطحوح ابتدایی تا بسیار پیشرفته را پوشش داده است لذا هم به عنوان کتاب درسی دانشگاهی و هم به عنوان کتاب مرجع مهندسین قابل استفاده است.
فهرست مندجات:
Preface
1 Introduction
1.1 Modern digital design
1.2 CMOS technology
1.3 Programmable logic
1.4 Electrical properties
Summary
Further reading
Exercises
2 Combinational logic design
2.1 Boolean algebra
2.2 Logic gates
2.3 Combinational logic design
2.4 Timing
2.5 Number codes
Summary
Further reading
Exercises
3 Combinational logic using VHDL gate models
3.1 Entities and architectures
3.2 Identifiers, spaces and comments
3.3 Netlists
3.4 Signal assignments
3.5 Generics
3.6 Constant and open ports
3.7 Testbenches
3.8 Configurations
Summary
Further reading
Exercises
4 Combinational building blocks
4.1 Three state buffers
4.2 Decoders
4.3 Multiplexers
4.4 Priority encoder
4.5 Adders
4.6 Parity checker
4.7 Testbenches for combinational circuits
Summary
Further reading
Exercises
5 Synchronous sequential design
5.1 Synchronous sequential systems
5.2 Models of synchronous sequential systems
5.3 Algorithmic state machines
5.4 Synthesis from ASM charts
5.5 State machines in VHDL
5.6 VHDL Testbenches for state machines
Summary
Further reading
Exercises
6 VHDL models of sequential logic blocks
6.1 Latches
6.2 Flip-flops
6.3 JK and T flip-flops
6.4 Registers and shift registers
6.5 Counters
6.6 Memory
6.7 Sequential multiplier
6.8 Testbenches for sequential building blocks
Summary
Further reading
Exercises
7 Complex sequential systems
7.1 Linked state machines
7.2 Datapath/controller partitioning
7.3 Instructions
7.4 A simple microprocessor
7.5 VHDL model of a simple microprocessor
Summary
further reading
Exercises
8 VHDL simulation
8.1 Event-driven simulation
8.2 Simulation of VHDL models
8.3 Simulation modelling issues
8.4 File operations
Summary
Further reading
Exercises
9 VHDL synthesis
9.1 RTL synthesis
9.2 Constraints
9.3 Synthesis for FPGAs
9.4 Behavioural synthesis
9.5 Verifying synthesis results
Summary
Further Reading
Exercises
10 Testing digital systems
10.1 The need for testing
10.2 Fault models
10.3 Fault-oriented test pattern generation
10.4 Fault simulation
10.5 Fault simulation in VHDL
Summary
Further reading
Exercises
11 Design for Testability
11.1 Ad hoc testability improvements
11.2 Structured design for test
11.3 Built-in self-test
11.4 Boundary scan (IEEE 1149.1)
Summary
Further reading
Exercises
12 Asynchronous sequential design
12.1 Asynchronous circuits
12.2 Analysis of asynchronous circuits
12.3 Design of asynchronous sequential circuits
12.4 Aysnchronous state machines
12.5 Setup and hold times and metastability
Summary
Further reading
Exercises
13 Interfacing with the analogue world
13.1 Digital to analogue converters
13.2 Analogue to digital converters
13.3 VHDL-AMS
13.4 Phased-locked loops
13.5 VHDL-AMS simulators
Summary
Further reading
Exercises
Appendix A VHDL standards
Appendix B Verilog
Appendix C Shared variable packages
Bibliography
Answers to selected exercises
Index
